It’s a Tuesday, and you’re sitting in a capacity planning meeting with a spreadsheet you built three weeks ago. Two hundred accelerator cards, phased across two quarters, with a per-card number you got from a vendor quote. Someone from procurement joins late, shares their screen, and the number is wrong. Not off by rounding. Off by 30%. The cards are the same cards. The quote is eight weeks old.
That’s roughly the situation a lot of infrastructure teams in China walked into this month. On September 10, Reuters reported that domestic AI chip prices have jumped 20% to 50% compared to quotes given to customers just two months earlier, depending on contract terms. The cause isn’t demand for the chips themselves. It’s the high-bandwidth memory stacked next to the compute.
The receipts
Huawei’s Ascend 950PR sold for around 60,000 yuan per card at the start of 2026. It now fetches more than 80,000 yuan. Cambricon repriced its next-generation part, tentatively called the 690, at 20% to 30% above what it had indicated two months prior. Smaller domestic players MetaX and Iluvatar CoreX have moved in the same direction.
The detail that should bother anyone doing long-range planning: this isn’t confined to new silicon. Older Ascend parts are caught in it too. When last year’s hardware gets more expensive, the usual escape hatch closes. You can’t just buy the previous generation and eat the performance hit, because the previous generation needs HBM too.
Zoom out and the picture gets less about China and more about memory. DRAM prices rose 90% in Q1 2026 alone versus Q4 2025, driven by an industry-wide pivot as Samsung, SK Hynix, and Micron shifted capacity. SK Hynix has warned the memory crunch may persist past 2030. Meanwhile, Chinese tech firms were told to move off Nvidia and onto home-grown accelerators, which concentrated demand onto exactly the domestic supply chain that has the least slack in its memory sourcing.
Why HBM is the constraint and not the footnote
If you’ve profiled inference workloads, you already know the punchline. Most serving traffic isn’t compute-bound. It’s memory-bandwidth-bound. Every decode step drags weights and KV cache across the memory bus, and the arithmetic units spend a good chunk of their life waiting. That’s why accelerator vendors keep stacking more HBM at higher bandwidth: it’s the part of the chip that actually determines your tokens per second under real request patterns.
Which means HBM isn’t a component you can substitute your way around. You can’t swap in slower memory and call it a downgrade, the way you’d accept a cheaper SSD tier for cold storage. Cut the bandwidth and you cut throughput close to linearly on the workloads that matter. The memory is the product.
What this changes for backend teams
The practical shift is that hardware cost stops being a fixed input to your architecture and becomes a variable you have to design against. A few things that follow from that:
- Quotes have a shelf life now. If your capacity model assumes a per-card price good for two quarters, it’s fiction. Build ranges, not point estimates, and re-derive your cost-per-million-tokens whenever procurement refreshes.
- Utilization is worth more than it was in January. An accelerator sitting at 35% average utilization was previously a tolerable inefficiency. At an 80,000 yuan replacement cost, idle silicon is the most expensive thing in your rack. Continuous batching, better admission control, and honest measurement of real occupancy pay for themselves faster than they used to.
- KV cache management moves up the priority list. Paged attention, cache eviction policies, prefix reuse across requests — anything that reduces bytes moved per token is now a hardware procurement strategy wearing a software hat.
- Quantization stops being a research project. Smaller weights mean less memory traffic per step and more model per card. If you’ve been deferring that work, the economics just moved.
- Heterogeneous fleets are the likely reality. When multiple domestic vendors are all raising prices unevenly, teams will buy whatever they can get. Your scheduler and your serving stack should not assume one accelerator SKU.
The uncomfortable part
Supply-driven price moves behave differently from demand-driven ones. Demand shocks reward you for waiting; someone eventually builds more capacity and prices come down. A supply constraint on a component with a handful of qualified producers and multi-year fab lead times doesn’t clear on a schedule that fits your roadmap. SK Hynix’s own warning about the timeline is the closest thing to guidance anyone’s offering.
The teams that come out of this in decent shape won’t be the ones who guessed the price curve. They’ll be the ones who got serious about squeezing throughput out of the cards they already own, because that’s the one variable still sitting inside their own repository. Memory bandwidth was always the real bottleneck in AI serving. It just stopped being free to ignore.
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